Categories: 102 Date: Jun 10, 2014 Title: In re Rambus: Reference Fails to Disclose a "value that is representative of an amount of time"
|Title||In re Rambus, Inc., No. 2013-1192 (Fed. Cir. June 4, 2014).|
|Issue||[Micron argues that] multiplexed lines in Fig. 25a [of prior art reference Bennet] cause a delay of known value (one clock cycle) before data transfer. Setting Parameter VI to 1 causes the lines to be multiplexed. Therefore, [according to Micron,] Parameter VI [discloses] a “value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.”|
In re Rambus, Inc. at *7 (text added).
|Holding||Parameter VI is only “representative” of one source of delay because the actual delay can be longer due to other factors. [Since changing Parameter VI does not necessarily create a one clock cycle delay], Parameter VI is not a “value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.”|
Id. at *8 (text added).
|Procedural History||This is an appeal from an inter partes reexamination of claims 26 and 28 of U.S. Patent No. 6,426,916 (“the ’916 patent”). The Patent Trial and Appeal Board (“Board”) at the United States Patent and Trademark Office (“PTO”) found that the claims were anticipated by U.S. Patent No. 4,734,909 to Bennett (“Bennett”). Patent owner Rambus, Inc. (“Rambus”) appeals the Board’s anticipation decision, arguing that Bennett does not disclose the claimed “value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.”|
In re Rambus, Inc. at *2.
|Legal Reasoning (Rader, Moore, Reyna)|
|Claim 26||A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising:|
clock receiver circuitry to receive an external clock signal;
first input receiver circuitry to sample block size information synchronously with respect to the external clock signal, wherein the block size information is representative of an amount of data to be output by the memory device in response to a first operation code;
a register which stores a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data;
a plurality of output drivers to output the amount of data in response to the first operation code and after the amount of time transpires.
In re Rambus, Inc. at *4.
|Bennet and its Parameter VI||The Board relied on Figs. 25a and 25b in Bennett, and the related “Parameter VI.” These figures are schematic representations of operations occurring on a memory bus. Parameter VI is the internal parameter in Bennett that determines whether the data and wait lines in these figures are dedicated or multiplexed. Specifically, when Parameter VI is 1 (as in Fig. 25a), these lines are multiplexed, and when it is 3 (as in Fig. 25b), each signal has a dedicated line. As explained in more detail below, the data transfer in Fig. 25a takes place one clock cycle later than the data transfer in Fig. 25b.|
Id. at *6.
|Legal Standard: Anticipation||A patent is anticipated “if a single prior art reference discloses each and every limitation of the claimed invention.” Schering Corp. v. Geneva Pharm., 339 F.3d 1373, 1377 (Fed. Cir. 2003) (citing Lewmar Marine, Inc. v. Barient, Inc., 827 F.2d 744, 747 (Fed. Cir.1987). Anticipation is a question of fact reviewed for substantial evi- dence. See In re Baxter Travenol Labs., 952 F.2d 388, 390 (Fed. Cir. 1991).|
Id. at *5.
|Factors affecting "amount of time"||[A]rbitration may take an indeterminate amount of time because a memory device may “lose” arbitration on successive occasions. If arbitration in Fig. 25b happens to take longer than in Fig 25a, the memory system with multiplexed lines (Fig. 25a) may actually have less delay before data transfer. Similarly, a busy memory device with dedicated lines may have a longer delay, due to wait signals, than an available device with multiplexed lines. Because of these two additional, indefinite, sources of delay, changing Parameter VI from 1 to 3 will not produce a set amount of time after which data is transferred. Therefore, Parameter VI is not “representative” of an amount of time after which data is transferred.|
In re Rambus, Inc. at *8.
|Value cannot Represent "amount of time" if there are other variable in play||The Board found that, in at least some embodiments in Bennett, Parameter VI meets the claim limitation at issue. Specifically, when the embodiments in Fig. 25a and b both (1) win arbitration on the first attempt and (2) are not busy for an indeterminate amount of time, then Parameter VI is a “value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.” We disagree. A value cannot “represent” an “amount of time” if there are additional factors, wholly unrepresented by that value, that necessarily impact, or represent, the “amount of time.” |
Id. at *8.
|Accordingly, we reverse the Board’s decision that Bennett anticipates claims 26 and 28 of the ’916 patent.|
In re Rambus, Inc. at *9.